The present invention relates to a semiconductor memory device. More specially, the present invention relates to a semiconductor memory device and a repair method thereof which can manufacture a semiconductor memory device having the large capacity into a semiconductor memory device having the small capacity.
It is very important to reduce a chip size without reducing manufacturing process even in case that the capacity of a semiconductor memory device is increased. However, in some devices, a chip size can not be reduced even though process are reduced. The increase of the number of pads has an effect on a chip size. That is, if the number of pads is increased, the area occupied by the pads is increased so that the chip size can not be reduced. Specially, a chip size can not be reduced due to the increase of the number of pads in case of a semiconductor memory device having a lot of data input/output pins.
For example, in case memory cells each having the capacity of N, 2N and 4N are manufactured in a semiconductor memory device through a manufacturing process P1, the chip size of the memory cells is S, 2S and 4S, respectively. However, in case memory cells each having the capacity of 2N and 4N are manufactured in a semiconductor memory device through a manufacturing process P2, the chip size is reduced to S and 2S, respectively. And in case a memory cell having the capacity of 4N is manufactured in a semiconductor memory device through a manufacturing process P3, the chip size is reduced to S. That is, the manufacturing process is simplified to P1, P2 or P3 according to the capacity of memory cells increasing to N, 2N or 4N. A semiconductor memory device with memory cells having the capacity of 4N is manufactured as having the size of 4N through the manufacturing process P1. If manufactured through the process P2, a semiconductor memory device has the size of 2N. A semiconductor memory device has the size of N through the process P3. That is, a semiconductor memory device with memory cells having the capacity of N, 2N or 4N is manufactured into a semiconductor memory device having the size of S by the process P1, P2 or P3.
The process P1 can manufacture a semiconductor memory device which the capacity of memory cells is N, 2N or 4N. The process P2 can manufacture a semiconductor memory device which the capacity of memory cells is 2N or 4N. The process P3 can manufacture a semiconductor memory device which the capacity of memory cells is 4N. That is, it is not impossible to manufacture a semiconductor memory device having the small capacity by using the updated process. That is why a chip size can not be reduced enough to improve the productivity. Accordingly, process for manufacturing a semiconductor memory device which the capacity of memory cells is N, 2N or 4N is different from one another.
However, if a semiconductor memory device having a first capacity manufactured by a first process can be manufactured into a semiconductor memory device having a second, smaller capacity using the same process, then the semiconductor memory device having the second, smaller capacity of an identical physical size can be manufactured even though a different process is not adopted.
In addition, in situations in which only some partial blocks of a semiconductor memory device comprising a plurality of memory cell array blocks are defective, if only normal partial blocks, excluding defective blocks, could be manufactured into a semiconductor memory device having a second, smaller capacity, the yield of the semiconductor memory device could be improved.
In accordance with one embodiment of the present invention, a semiconductor memory device is provided which comprises a plurality of memory cell array blocks, each including a plurality of partial blocks selectable by n address bits from a plurality of address bits. A partial block select signal generator generates address bits to select a subset of the partial blocks from the plurality of partial blocks in each of the plurality of memory cell array blocks.
According to another aspect of the present invention, a semiconductor memory device is provided which includes a plurality of memory cell array blocks, each including a plurality of partial blocks selectable by n address bits from a plurality of bits address. A partial block select signal generator generates partial block select signals for selecting one-fourth of the partial blocks in each of the plurality of memory cell array blocks by establishing a state of corresponding address bits among the n address bits. The partial block select signal generator further includes means for selecting one-fourth of the partial blocks in each of said plurality of memory cell array blocks by establishing a state of a first address among the n address bits.
In yet another aspect of the invention, a method is provided for repairing a semiconductor memory device having a plurality of memory cell array blocks each including 2n partial blocks selectable in response to n bits address among a plurality of bits address. The method comprises selecting xc2xdn partial blocks of the 2n partial blocks in each of the plurality of memory cell array blocks by selecting the state of corresponding address bits among the n address bits.